1. Field of the Invention
This disclosure relates to semiconductor integrated circuit devices, and, in particular, to a semiconductor memory device that supports a continuous burst read mode of operation.
2. Description of the Related Art
Presently, many semiconductor memory devices (e.g., SRAM, DRAM, flash memories, and so forth) support a burst read mode of operation, or burst mode, in which data is continuously read out from a given start address synchronized with a clock signal from the external. In the burst mode, a constant delay time is needed until the first data is outputted from a memory device after a start address is inputted to the memory device. The clock number corresponding to the delay time is commonly called “latency” or “standby time”. During the delay time, a sense amplifier circuit senses data from memory cells and the sensed data is temporarily stored in a register. Afterwards, data thus stored is outputted to the external through an output buffer circuit in synchronization with a rising and falling edge of a clock signal.
In case of an asynchronous or random access type in which data corresponding to an address is outputted whenever the address is inputted from the external, a semiconductor memory device includes as many sense amplifiers as the number of data lines. Unlike the random access type, a burst read type of semiconductor memory device reads out data corresponding to a burst length immediately and the read-out data is loaded on a data bus by one group. For this reason, the semiconductor memory device of the burst read type requires plural groups of sense amplifiers. Thus, in case of a semiconductor memory device supporting a burst read operation, the number of necessary sense amplifiers is determined by the number of data lines and the burst length.
While data is outputted to the external through one burst cycle, it is capable of outputting data of the next burst cycle without latency by reading out data of the next burst cycle and temporarily storing the read-out data in a register. This operation is referred to as a continuous burst read operation. With this continuous burst read operation, a semiconductor memory device can successively read out data from any address to the end of an address space. Accordingly, the continuous burst read operation enables a large volume of continuous data to be accessed at a high rate of speed.